NATURE: A Hybrid Nano/CMOS Dynamically Reconfigurable System

NATURE: A Hybrid Nano/CMOS Dynamically Reconfigurable System

Abstract:

As CMOS technology approaches its physical limits, a tremendous amount of efforts are being devoted to nanotechnology research in order to enable future technology scaling. Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet mature. Implementing nanocircuits on a large scale is still infeasible in the near future. On the other hand, if photo-lithography could be used to implement circuits using these nanodevices, then hybrid nano/CMOS chips could be fabricated immediately.

This talk will present a high-performance reconfigurable system, called NATURE, which utilizes a hybrid of nano RAMs and CMOS logic. Examples of nano RAMs that can be used in NATURE are nanotube RAM, phase-change memory and magnetoresistive RAM. The high density of nano memory allows large-capacity on-chip reconfiguration bit storage and its high performance supports fast access. It enables reconfiguration of each logic block through its associated reconfiguration memory at the cycle level with a small reconfiguration delay (only around hundreds of picoseconds). This means each logic block can be reused to implement different functions every clock cycle. Thus, circuits can be folded into a sequence of logic stages to temporally share the same hardware resources, called logic folding, which saves area proportionately to the circuit logic depth. Logic area reduction also results in a reduced need for a deep interconnect hierarchy and, hence, saves routing area. With only 20% area overhead incurred for nano memories and 10% delay overhead for reconfiguration delay, the fine-grain cycle-level reconfiguration increases logic density by a factor of 27X, and increases the logic block utilization up to 100%. A 10X improvement in area-delay product and 2X power reduction can be obtained compared to traditional FPGA implementations. This means that a million-gate application, which originally requires a Xilinx Virtex-5 that costs thousands of dollars, is now able to be accommodated in Spartan for less than a hundred dollars.

An integrated design and optimization platform for NATURE, called NanoMap, will also be presented in this talk. The platform fully facilitates logic folding and automatically maps and evaluates a specific design in the cycle-level reconfigurable architecture. NanoMap conducts design optimization from the register-transfer level (RTL) or gate level down to the physical level using novel mapping methodologies. Given a design, it automatically explores and identifies the best temporal logic folding configuration, targeting user-defined area/delay optimization objectives, and implements the design through several steps including logic mapping, temporal clustering, temporal placement, and routing. During logic mapping, a force-directed scheduling technique is used to balance resource usage across different clock cycles, minimize overall resource usage, and optimize performance under constraints. The following steps consider resource sharing and temporal data storage across clock cycles during clustering, placement, and routing. NanoMap grants the designer superior flexibility to perform area-delay trade-offs and satisfy various requirements through using different logic folding configurations for one application.