Power Aware High Performance Microprocessor Design Challenges

Power Aware High Performance Microprocessor Design Challenges

Abstract:

With the increasingly large number of transistors on modern day microprocessors, transistor real estate is becoming cheaper and feature sets are growing larger. The ability to increase the performance of these machines is becoming almost independent of the underlying instruction set architecture and the focus is increasingly in the core and memory architecture and their power aware implementations in deep sub micron technologies. In this presentation, we will discuss the instruction set consolidation and the challenges in implementing these complex designs in sub 65nm processor technologies.