Synthesis of Sequential Circuits with Clock-Control to Improve Testability

Synthesis of Sequential Circuits with Clock-Control to Improve Testability

Abstract

A test-vector sequence for a sequential circuit can be viewed as a sequence of subsequences each of which has three tasks. Justification: moving from the last state to the state where next test can be applied, Test: application of the test pattern, Propagation: leading the erroneous signal to a primary output.
A scan-capable circuit can perform justification (step 1) in log N (N = number of states) steps and propagate in one step. In functional testing, passage into illegal states is not allowed so scan cannot be used. In this situation a poorly connected Finite-State-Machine can, in the worst case, require O(N) steps for justification.
In this talk we will discuss a method to improve the graph connectivity by controlling the clock without modifying the underlying FSA of the circuit. I will present a state-encoding scheme which, in conjunction with the clock-control, has O(log N) time bound for justification without entering an illegal state.