A Performance Study of Memory Consistency Models

A Performance Study of Memory Consistency Models

Abstract

Recent advances in technology are such that the speed of processors is
increasing faster than memory latency is decreasing. Therefore the
relative cost of a cache miss is becoming more important. However, the
full cost of a cache miss need not be paid every time in a multiprocessor.
The frequency with which the processor must stall on a cache miss can
be reduced by using a relaxed model of memory consistency. 

In this paper, we present the results of instruction-level simulation
studies on the relative performance benefits of using different models
of memory consistency. Our vehicle of study is a shared-memory
multiprocessor with processors and associated write-back caches
connected to global memory modules via an Omega network. The benefits
of the relaxed models, and their increasing hardware complexity, are
assessed with varying cache size, line size, and number of processors.
We find that substantial benefits can be accrued by using relaxed
models bu the magnitudes of the benefits depends on the architecture
being modeled, the benchmarks, and how the code is scheduled. We did
not find any major difference in levels fo improvement among the
various relaxed models.