ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA -136119 SUMMER TRAINING On FPGA BASED DESIGN

ELECTRONICS AND COMMUNICATION ENGINEERING DEPARTMENT NATIONAL INSTITUTE OF TECHNOLOGY KURUKSHETRA -136119 SUMMER TRAINING On FPGA BASED DESIGN USING VERILOG HDL (June 15 to July 24, 2009)

IMPORTANT DATES:

Last date for Submission of registration form: 22nd May. 2009.

• Intimation of acceptance (on website): on or before 29th May, 2009.

ECE department, equipped with state-of-the art VLSI facilities, announces a summer training on “ FPGA BASED DESIGN USING VERILOG HDL ”, during June 15 to July 24, 2009.

The training is motivated by accelerated industrial growth in the new area of programmable logic. Our aim is to train the participating students on FPGA targeted digital design using VERILOG. They will work on industry oriented projects . Series of lectures , intensive hands-on exercises, and lab sessions ( on Verilog, Xilinx tools and FPGAs architectures) have also been embedded into the training programme to facilitate the students in understanding various design aspects of programmable logic.

Enrollment is limited to 30. So early participants will be given preference. The intended participants must have affinity towards digital system design, HDLs, EDA tools, and applications of FPGAs.

INTRODUCTION:

The developments in electronics and communication engineering in the last few decades have been almost totally in the area of VLSI. The developments in programmable and configurable designs have resulted in unprecedented pace of growth in VLSI and other areas of electronics and communication engineering.The department of electronics and communication engineering of NIT Kurukshetra is presently participating in project SMDP-II (Special Manpower Development Programme in VLSI design and related software), funded by ministry of IT government of India. Under the project, the department has undertaken to generate manpower in VLSI design at different levels (UG, PG and Ph.D).

The VLSI Design Lab (under SMDP-II) is well equipped with latest VLSI CAD tools and FPGAs boards.

OBJECTIVE OF THE PROGRAMME:

The objective of this programme is to impart hands on training to the students on FPGA based digital design using Verilog HDL. The training programme aims at providing a detailed view of programmable design flow. The

training emphasizes on hands on experience of digital design and its implementations on Xilinx boards-SPARTAN-3E & VIRTEX-II PRO.

Address for Correspondence:

Dr. R.K.Sharma, Coordinator SMDP-II

ECE Department, NIT Kurukshetra-136 119

Ph: 01744-233-419 (O), Mob: 09896688346

Email: mail2drrks@gmail.com