DISTRIBUTED LOW POWER EMBEDDED SYSTEM

DISTRIBUTED LOW POWER EMBEDDED SYSTEM

Abstract

Dynamic voltage scaling (DVS) is one of the most studied topics in low-power embedded systems. Based on CMOS characteristics, the power consumption is proportional to V2; while the supply voltage V is linearly proportional to the clock frequency. To fully exploit such quadratic power vs. voltage scaling effects, previous studies have extensively explored DVS with real-time and non-real-time scheduling techniques. As DVS reaches its limit on a single processor, researchers turn to multiple processors to create additional opportunities for DVS. Multiple processors can potentially achieve higher energy savings than a single processor. By partitioning the workload onto multiple processors, each processor is now responsible for only a fraction of the workload and can operate at a lower voltage/frquency level with quadratic power saving. Meanwhile, the lost performance can be compensated by the increased parallelism. Another advantage with a distributed scheme is that heterogeneous hardware such as DSP and other accelerators can further improve power effi- ciency of various stages of the computation through specialization. Although a tightly-coupled, shared-memory multiprocessor architecture may have more power/performance advantages, they are not as scalable as distributed, messagepassing schemes. While distributed systems have many attractive properties, they pay a higher price for message-passing communications. Each node now must handle not only I/O with the external world, but also I/O on the internal network. Programming for distributed systems is also inherently more difficult than for single processors. Although higher-level abstractions have been proposed to facilitate distributed programming, these abstraction layers generate even more inter-processor communication traffic behind the scenes. While this may be appropriate for high-performance cluster computers with multi-tier, multi-gigabit switches like Myrinet or Gigabit Ethernet, such high-speed, high-power communication media are not realistic for battery-powered embedded systems. Instead, the low-power requirement have constrained the communication interfaces to much slower, often serial interfaces such as I2C and CAN. As a result, even if the actual data workload is not large on an absolute scale, it appears expensive relatively to the computation performance that can be delivered by today’s lowpower embedded microprocessors. The effect of I/O on embedded systems has not been well studied in existing DVS works. Many existing DVS techniques have shown impressive power savings on a single processor. However, few results have been fully qualified in the context of an entire system. Even fewer have been validated on actual hardware. One common simplifying  assumption is to ignore I/O.

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