Three Days Workshop on Xilinx FPGA solutions for image and signal processing applications

Three Days Workshop

 on

Xilinx FPGA solutions for image and signal

processing applications

4th, 5th &6th April 2013

Organized by

TIFAC - CORE in AUTOMOTIVE INFOTRONICS

(Sponsored by Department of Science and Technology, Govt. of India)

Coordinators

Dr. K. Ganesan, Director, TIFAC CORE & Senior Professor, SITE

D. Muralidar, Assistant Professor, TIFAC CORE

D.Sridhar, Development Engineer, TIFAC CORE

TIFAC-CORE IN AUTOMOTIVE INFOTRONICS @VIT

·        State of the art advanced engineering Centre for research, consultancy and manpower excellence in Automotive Infotronics is established at VIT University promoted by TIFAC (Technology Information Forecasting and Assessment Council), under the Mission REACH program.

·        Offers a full time M. Tech. program in Automotive Electronics to provide industry ready engineers.

CoreEL UNIVERSITY PROGRAM

CoreEL university program as the name suggests, has a mandate to reach out to the larger talent pool in the Indian universities. It comprises of dedicated team of professionals who possess rich design and application engineering experience in VLSI, embedded and related areas. With its core team in Bangalore and regional offices in key cities across the country, the university solution groups draw its strength from its established design service teams and from sandeepaniIndia’s no.1 VLSI design school. The groups association with world leaders such as Xilinx, mentor graphics, wind river,(works),kontran,MATLAB(math works) and speedgoad,real-time simulation tools solutions makes it a formidable force in providing solutions in the university space.CoreEL university program offers distribution of world class VLSI development platforms and EDA tools to academia communities which includes

·        VLSI lab infrastructure setup assistance as per course curriculum of institutions

·        EDA tools installation and enabling tool utilization through customized training offerings

·        Domain specific workshop modules to address the requirements of research enthusiasts

·        Technical support services for academia communities in their R&D activities

Background

VLSI expertise team comprises Faculty Members and Engineers from TIFAC-CORE will share their knowledge and experience on Image Processing and Xilinx DSP blockset. The students will be allowed to use selected software and hardware facilities available at TIFACCORE laboratory to gain real time knowledge on Basic Digital Image Processing (DIP) Techniques using Spartan 6 FPGA.

Topics to be covered:

Day1:

• ·        Introduction to Digital Image Processing
• ·        Image Enhancement Techniques
• ·        Histogram Equalization
• ·         Edge Detection
• ·        Image scrambling
• ·         Lab: Hands on session of image processing algorithms

Day2:

• ·         Need of FPGAs for addressing high-performance DSP designs
• ·         Introduction to Xilinx System Generator for DSP
• ·         Concepts of system modeling using Simulink
• ·         Overview of Xilinx block sets and system modeling forhardware implementation
• ·        Model and simulate a DSP block using Simulink/ Xilinx System generator
• ·        Lab: Getting started with Simulink
• ·        Lab: Creating a 12 x 8 MAC Using the System Generator for DSP
• ·        Lab: Signal Routing – custom system modeling for DSP applications

Day3:

• ·        Concepts of Hardware co-simulation using System Generator DSP
• ·        Lab : Implementing a system controller as per the design specifications
• ·        Lab : Designing a Multirate MAC FIR system
• ·        Lab: Hardware co-simulation of FIR filter using Virtex-5 FPGA Evaluation platform
• ·        Addressing Video and image processing applications using Xilinx FPGA’s –Challenges and current trends
• ·        Lab: Demonstration of real time image processing application using Xilinx Spartan-6 & Virtex-5 FPGA Development platforms
•  

Targeted participants

·        Faculties/Research Scholars

·        Students

·        Working Professionals

Registration fees:

Rs. 2250 per delegate from Institute (Student)

Rs. 3400 per delegate for research scholars/Faculties

Rs. 4500 per delegate for working professionals

Registration charges include Hand-outs, Lunch & Tea. The number of participants is limited to 30 based on first come first serve.

Venue& Date:

Hall No.: 701, Technology Tower

7th Floor, VIT

4th, 5th& 6th April 2013: 09.30 – 17.00 Hours

For Technical details contact:

Mr.D.Muralidar                                      Mr.D.Sridar

Asst.Professor                                        Development Engineer

TIFAC CORE                                            TIFAC CORE

Mobile: 9894335864                            Mobile: 9940555944

Landline: 0416-2202384                     sridhar.d@vit.ac.in

muralidar.d@vit.ac.in