Short Term Course on VLSI Signal Processing 27th November - 1st December, 2009

Short Term Course on VLSI Signal Processing 27th November - 1st December, 2009

Coordinator

Prof. Mrityunjoy Chakraborty
Dept of E & ECE
Indian Institute of Technology
Kharagpur-721302 (West Bengal), INDIA
Phone: 91-3222-283512 (O)
91-3222-283513 (R)
Email:mrityun@ece.iitkgp.ernet.in

COURSE OVERVIEW

Preface

Course summary : The course aims at providing a comprehensive coverage of techniques for designing efficient DSP architectures. Towards this, architectural optimization both at block level as well as logic level are considered. The objective is to realize architectures that can process high throughput data and/or require less power and/or less chip area. At block level, algorithmic transformation techniques like retiming, pipelining, parallel processing, systolic arrays, folding, unfolding etc. are considered. Examples from real life signal processing and communications are taken up. Also both word level and bit level architectures are presented. At logic level, design of various datapath elements starting from high speed adders to complex CORDIC blocks is outlined. Logic level as well as circuit level optimization for multi objective functions involving speed, area and power are discussed in detail for various application domains. Issues pertaining to the design of mixed signal chips are also be touched upon.
The course may be viewed as a consolidated form of a semester long, graduate course on VLSI DSP system/architecture design. Participants from academia may thus find the course to be useful to develop similar courses at their respective institutions. Alternatively, the course may also be used as a reference by industrial professionals interested in VLSI design of signal processing and communication systems. The course assumes minimal prerequisites - an undergraduate level knowledge of digital circuit design and elementary DSP operations is sufficient for one to be able to attend the course.

Contents :

Part A : VLSI Architecture for Signal Processing – Optimization by High Level Transformations, by Prof. Mrityunjoy Chakraborty
• Graphical representation of DSP algorithms – signal flow graph (SFG), data flow graph (DFG), critical path, dependence graph (DG).
• Retiming – properties, cutset retiming and pipelining, retiming in a loop, iteration bound
• Parallel processing via unfolding of a DFG
• Folding and hardware optimization
• CORDIC algorithm and multiplier less architectures
• Introduction to Systolic Arrays

Part B : Design of VLSI Architectures for Digital Signal Processing : Optimization at Logic Level by Prof. A. S. Dhar
• Architectural Design at Register Transfer Level
• Design of Datapath elements
• Control structures
• Testable and self-reconfigurable fault-tolerant structures
• Speed-Area-Power tradeoff
• Issues related to mixed signal design and SoC

Scope of the Course

The course aims at providing a comprehensive coverage of techniques for designing efficientDSP architectures. Towards this, architectural optimization both at block level as well as at logic level will be considered. The objective is to realize architectures that can process high throughput data and/or require less power and/or less chip area. At block level, algorithmic transformation techniques like retiming, pipelining, parallel processing, systolic arrays, folding, unfolding etc. will be considered. Examples from real life signal processing and communications will be taken up. Also both word level and bit level architectures will be presented. At logic level, design of various datapath elements startingfrom high speed adders to complex CORDIC blocks will be outlined. Logic level as well as circuit level optimization for multi objective functions involving speed, area and power will be discussed in detail for various application domains. Issues pertaining to the design of mixed signal chips will also be touched upon.

The course may be viewed as a consolidated form of a semester long, graduate course on VLSI DSP system/architecture design. Participants from academia may thus find the course to be useful to develop similar courses at their respective institutions. Alternatively, the course may also be used as a reference by industrial professionals interested in VLSI design of signal processing and communication systems. The course assumes minimal prerequisites - an undergraduate level knowledge of digital circuit design and elementary DSP operations is sufficient for one to be able to attend the course.


About the Speakers

Prof. Mrityunjoy Chakrabortyobtained Bachelor of Engg. (1983), M.Tech. (1985) and Ph.D. (1994) from Jadavpur University, IIT Kanpur and IIT, Delhi respectively. He joined IIT, Kharagpur as a lecturer in 1994, where he presently holds the position of a full professor. Prof. Chakraborty has held many invited, visiting positions in reputed universities abroad. He is currently an associate editor of the IEEE Transactions on Circuits and Systems, Part II. Earlier, he served as an associate editor of the IEEE Transactions on Circuits and Systems, Part I (2004-2007), as a guest editor of the EURASIP JASP and a TPC member for many important IEEE conferences. The teaching and research interests of Prof. Chakraborty are in digital and adaptive signal processing, VLSI signal processing, wavelets and DSP for wireless communications, in which he has guided several Ph.D. students and published extensively.

Prof. Anindya Sundar Dhar obtained Bachelor of Engg. in Electronics and Telecomm.Engg.from Bengal Engg. College (1987), followed by M.Tech. (1989) and Ph.D. (1994) from IIT Kharagpur. He is presently an associate professor in Electronics and Electrical Communication Engg., with teaching and research interests in VLSI architecture design for real time signal processing and communication. Prof. Dhar is a key person in the various VLSI related activities in the institute and has been offering many challenging courses in this area over years, apart from carrying out guided, independent and sponsored research in the above areas.

Registration Form


Registration Fees

• Rs. 8500.00 for teachers from universities/ colleges.
• Rs. 12,000.00 for people from industry.
• Rs. 5500.00 for students/research scholars [please enclose a bonafide certificate from parent institution].
** Registration fee includes accomodation, breakfast and all meals, course material and course fees.

Important Dates

Last date for registration : 31st October, 2009 [Complete application should be received by the coordinator by this date]
Registration Deadline Extended to 7th November 2009

How to Apply :

Interested persons may apply in the format given herewith along with the registration fee, paid through a demand draft drawn in favour of ‘CEP-STC, IIT Kharagpur’ and payable at Kharagpur. The number of seats is limited and thus candidates are advised to register early.

About IIT, Kharagpur

The IIT is located at Kharagpur, an important railway town about 116 km west of Kolkata.
Kharagpur is well connected to almost all part of the country by train. There are frequent train services from Howrah railway station to Kharagpur. The institute is about 5 km away from Kharagpur station and can be reached by taxis, auto-rickshaws, cycle-rickshaws etc. IIT, Kharagpur is the oldest IIT in the country and is the first among equals in terms of diversity in curricular as well as extra-curricular activities.

Contacts :

Prof. M. Chakraborty, Prof. A. S. Dhar
Dept. of E. & E.C.E., IIT, Kharagpur 721302
Email : mrityun@ece.iitkgp.ernet.in
asd@ece.iitkgp.ernet.in
Phone : 03222-283512 (O), 283516 (O)
03222-283513 (R), 283517 (R)